A Novel Architecture for Vliw Processor

Technology has seen the development of processor industry right from micro to the latest Nanotechnology with speed being important criteria. Not much attention has been given to the power required to drive these Integrated Circuits. With gaining popularity in mobile computing, developing mobile processors have gained popularity since these processors possess unique properties like low power consumption and dissipation. This paper aims at designing a low power Very Long Instruction Word (VLIW) processor with built in FFT processor, which uses single clock frequency. This VLIW processor is designed with two modules one for VLIW processor and the other one is Hybrid dynamic voltage scaling module. Using the DVS algorithm the power can be reduced up to 20 to 25 % of normal VLIW processor. The design is simulated and synthesized using Xilinx project Navigator and the report is given in the paper. Keyword: VLIW processor, VHDL, interDVS, intraDVS, Hybrid DVS etc.,